1. Field of the Invention
The present invention relates to a manufacturing method for an integrated semiconductor structure.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology.
In modern DRAM memory circuits, it is an ongoing demand to process electronic devices in a memory cell region and electronic devices in a peripheral device region as effectively as possible. Since the electronic devices of both regions require different processing, it is not always possible to process them simultaneously.
It is generally known to provide gate stacks which are covered with insulating caps surrounding the electrical conductive gate conductors, which caps comprise a plurality of isolation layers. Hereinafter, the expression cap is used to define one or more insulation layers surrounding the electrical conductive gate conductors which may be present on top of and/or surrounding the electrical conductive gate conductors.